In an Out-Of-Order (“OOO”) microprocessor, instructions are allowed to issue out of their program order. However, in most cases, they are required to retire from the machine in order. Further, memory operations in the machine, regardless of the issue order, need to acquire and update memory status in program order. These diverging ordering behaviors give rise to problems at several locations in a micro-architecture.
For example, in an OOO microprocessor, the instructions executing out of order need to preserve their data dependence constraints. Because instructions may finish in an arbitrary order, the architectural register file cannot be modified by the instructions as they finish because it would make it difficult to restore their values accurately in the event of an exception or an interrupt. To achieve high performance, register renaming is commonly used with the temporary register storage to allow the OOO processor to resolve false dependencies between instructions. Hence, every instruction that enters the pipeline is provided a temporary register where it can save its result. The temporary registers are eventually written into the architectural register file in program order. Thus, even though instructions are being executed out of order, the contents of the architectural register files change as though they were being executed in program order.
The architectural register file is typically maintained in the back-end of the OOO processor. As a result of using temporary register storage along with register renaming, instructions with write-after-write (WAW) and write-after-read (WAR) hazards can be issued out-of-order in conventional OOO processors.
There are cases in OOO microprocessor design where a value generated from a General Purpose Register (“GPR”), an architectural register also maintained at the back-end of the machine, could determine the control flow of the program (in the case of indirect branches), or could cause instructions or data values to be treated differently. In conventional OOO processors, instructions following a state producing instruction involving a GPR need to wait for the state producing instruction to get committed before being able to use its value. As a result, the process of executing instructions or even fetching new instructions becomes a serial process dependent on the execution of the state producing instruction getting committed to a quiescent state, which is visible to every microprocessor module that is affected by it. This serialization can introduce significant delays in the pipeline and diminish microprocessor performance.